Brian Bailey Consulting

Brian Bailey Consulting


I was born in England and lucky enough to attend Brunel University (in West London) for my undergraduate studies in Electrical and Electronic Engineering, receiving a 1st class honours degree in 1981. While at Brunel, I got involved in the development of a tool called HILO, the worlds first commercial RTL simulator and soon became part of the development team. I worked on a large number of parts of that simulator, finally becoming the project and engineering manager for it in 1987.

Following that I got back into the hardware side of things for a while, working on the development of a RISC processor but then migrated back into the EDA world by working on hardware accelerators at Zycad. At Zycad I designed a system that unified the companies multiple hardware and software platforms and provided graphical front end tools to those platforms. This required the development of waveform languages and display systems, waveform comparison and sophisticated debug tools. This group was later acquired by Synopsys where the work continued.

In 1992 I joined Mentor Graphics as the technical lead for their multi-level, mixed signal simulation environment, which included an extension of the C language for behavioral modeling in the hardware space. Extending the notion of mixed environments then took me into the hardware / software coverification space. With my role as technologist for this group, I also looked at it's extension into the system space, connection to emulators, embedded system development tools and many other directions. While the tool was successful capturing over 90% market share, cosimulation adoption was tepid. Wanting to learn more about the system design process, I started performing consulting to the Mentor's end user companies.

As a consultant, I developed some ideal reference flows, helped companies identify the bottlenecks in their own flows and advised them on the ways that they could make improvements. Coupled with this work was an extensive education program intended to help engineering teams understand the changes that were going on in the industry.

During the course of my work, I have had five patents issued and others pending. I have been involved in a lot of standards groups, starting with the development of VHDL value sets, System design methodologies and simulation backplane technologies for CFI, numerous standards within the system level group of VSI, which I also chaired for a number of years and chaired the C language semantics group of Accellera. I was the chair of the Accellera Interfaces Technical Committee which successfully developed a co-emulation standard.

An important aspect of my work has been communications, and teaching. This started out by being a participant in panels and later as moderator, keynote speaker, and presenting papers at conferences around the world. I have authored, co-authered or edited seven books , some of which have become seminal works in their field.

I am or have been a reviewer, technical program member or track chair for a number of conferences, including DATE, DAC and ESC. I established a functional verification track in DesignCon that quickly grew to become the track receiving most paper submissions while under my supervision.

Today, I spend most of my time as a journalist. I have written for EE Times, which I was the editor for the EDA Designline, EDN, Analog World and many others. Now I write for Semiconductor Engineering as their technical editor for EDA.

I have sat on several Technical Advisory Boards, many of which had successful exits. For example Jasper Design Automation, which was acquired by Cadence Design Systems, and Certess, which was acquired by Synopsys.

Helping companies improve their verification efficiency.

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