Brian Bailey Consulting

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In the News

Apr 2012 Power integrity -- How much does it matter?
Mar 2012 Time to rethink EDA flows and tool infrastructure
Mar 2012 Functional verification concepts have to change
Feb 2012 Analog_Bits_appear_everywhere_in_the_chip
Feb 2012 Speed kills when it comes to printed circuit boards or chips
Feb 2012 ChipEstimate.com New High for Litigation Low
Feb 2012 EDACafe: DVCon: You will be Tested
Jan 2012 Webinar: Power Issues for Chip and Board
Jan 2012 An interesting trend with EDA books
Jan 2012 EDA industry predictions for 2012
Dec 2011 Random problems associated with small geometries
Dec 2011 ESL: The value of abstraction
Nov 2011 The problem with the definition of ESL
Oct 2011 Ubiquitous Interfaces
Oct 2011 Does the EDA industry get any respect?
Sept 2011 Doing too much at once?
Sept 2011 Refreshingly different MathWorks
Sept 2011 Grappling with Model-Based Design
Aug 2011 Amr Mohsen – A story so bizarre…
Aug 2011 Dynamic reprogrammability seems rather static
Aug 2011 Am I Getting Old?
Aug 2011 Amazing but True
Aug 2011 Another one Bites the Dust - GateRocket
July 2011 Co-design – Myth or Reality?
July 2011 To the Virtual Prototype and Beyond
July 2011 Veridae had a Very Good Day
July 2011 Are you Positive about that Verification Approach?
June 2011 The Interface Roadblock
June 2011 Don’t listen to the experts. They have it backwards.
June 2011 A prediction ahead of its time?
June 2011 Art is important for our next generation of engineers
June 2011 Design Evolution locks you into Local Minima
May 2011 The DAC theme for 2011 will be…
May 2011 Stimulus done right
May 2011 The simulator is no longer enough
Apr 2011 There is C, C and oh yes C
Apr 2011 My memory is not what it used to be
Apr 2011 Experts At The Table: Changes In Verification
Apr 2011 The ESL Edge: A Plethora of Hierarchies
Apr 2011 Cadence responds to the Synopsys FPGA prototyping book
Mar 2011 May you live in interesting times…
Mar 2011 Book Review: FPGA-Based Prototyping Methodology Manual
Feb 2011 Do we need a new FPGA structure for prototyping?
Feb 2011 Are there any FPGA tool developers out there?
Jan 2011 Another high-level synthesis company targeting FPGAs
Jan 2011 Fundamentals of Prototyping
Dec 2010 The ESL dilemma
Dec 2010 What will it take for FPGAs to become as ubiquitous as processors?
Nov 2010 What can be expected from the Accellera Unified Coverage Interoperability Standard? Ghost Written
Nov 2010 Emulator, accelerator, prototype – what’s the difference?
Oct 2010 To emulate or prototype?
Oct 2010 Time to working prototype
Sept 2010 Debugging FPGAs at full speed
Sept 2010 Are FPGA tools dumb?
  Grant martin reviews my latest book TLM-driven Design and Verification Methodology
July 2009
EDN: Cadence adds pieces to C-to-Silicon strategy
July 2009
Cadence Press Realease on their TLM-Driven Design and Verification Solution
Aug 2008
ChipDesignMag: what are the enablers of ESL?
July 2008
Book Review: Taxonomies for the ... Digital Systems
July 2008
Electronic Design: Hardware/Software Co-Design Comes Of Age
May 2008
Certess Offers Hands-on Tutorial at the Design Automation Conference
May 2008
Blog started on Chip Design Magazine
Apr 2008 Bailey and Hartmann: Assertions aus einem anderen Blickwinkel in Elektronik 12/07 voted best article of the year.
Mar 2008 SCDsource: Constrained random test struggles to live up to promises.
Mar 2008 D&R Imperas Unleashes Open Source Initiative to Establish Common, Open Standard for Multicore SoC Design
Feb 2008 SCDSource: Formal property checking -- what the users say
Feb 2008 SCDsource: Coverage metrics not enough, verification experts say
Jan 2008 Press release: Certess Closes 2007 with 3X Growth, More Than 25 Active Customer Sites in Four Continents
Dec 2007 SoCcentral: The Great EDA Cover-up
Nov 2007 SCDsource: Understanding coverage with multiple verification methods
Nov 2007 SCDsource: Verification coverage measures up to higher level
Nov 2007 EDA DesignLine: The Great EDA Cover-up
Oct 2007 Technology Book Review: Low Power Done Right
May 2007 EE Times: Transaction-level standard boosts acceleration
May 2007
EE Times: Accellera approves SCE-MI 2.0 to speed acceleration
May 2007
Press Release: Accellera Approves High Performance Electronic Design Verification Standard
Mar 2007
Release of ESL Design and Verification Book and discussion forum
Feb 2007
DesignCon Morsels by Gabe Moretti
Dec 2006
EDN: Risk reduction in a verification upgrade. Ambar Sarkar, Brian Bailey
Dec 2006
System Design Frontier: Next Generation EDA Companies
Nov 2006
System Design Frontier: Coverage
July 2006
System Design Frontier: A new entry in the space for Verification Plans
July 2006
Verification (Can you hear me now?) by Clive Maxfield
July 2006
Press release: Jasper Design Automation Unveils Free Tool for Easy Generation of Structured Verification Plans
July 2006
Flows: First glimpse of new book coming in 2007: ESL Design and Verification: A prescription for Electronic System Level Methodology
July 2006
Patent number 7072820 issued "Accessing state information in a hardware / software co-simulation"
June 2006
Guest Editorial in System Design Frontier: Will large EDA companies be relevant in an ESL era?
June 2006
Press release: Cadence offers 'first' transaction-based system verification
May 2006
EDA News Cafe: Buzz @ DAC
May 2006
EE Times: How Assertions can be used for Design
Apr 2006
SoC Central: Performance Is a Way to Differentiate
Apr 2006
System Design Frontier: Performance Is a Big Deal
Apr 2006
Springer publishes "Writing Testbenches using SystemVerilog" by Janick Bergeron
Mar 2006
IEEE D&T Book Review: Was it worth the wait? Yes!
Mar 2006
System Design Frontier: How to Ensure 100% Success Rate on Your Next Chip
Feb 2006
Poseidon Design Systems Appoints Brian Bailey as Chief Technologist
Feb 2006
Jasper Design Automation Names Brian Bailey As Technical Advisory Board Member
Feb 2006
DesignCon Paper co-authored with Carina Chiang - Why did my chip do that?
Feb 2006
DesignCon Best Paper Finalist- A Taxonomy for the Electronic System Level (ESL)
Feb 2006
DesignCon Best Paper Finalist- Innovation: Learning from the EDA Industry
Feb 2006
EETimes: ESL needs more work, panelists say
Feb 2006
EDN: An Engineer's Guide to DesignCon: Technical papers
Jan 2006
System Design Frontier: Understanding ESL
Nov 2005
ChipDesign Magazine: Numerous Approaches Tackle Design for Debug
Dec 2005
EETimes India: Wrestling with functional verification
Oct 2005
EE Times: Verification moves to a higher level
Aug 2005
EE Times: Easing verification challenges for IP reuse
Aug 2005
VSIA: Standard Who's Time Has Come?
June 2005
EDA Confidential: This Verification Crisis is of Our Own Making
June 2005
EDA Confidential: Lies, Damn lies and Statistics
May 2005
EE Times: Accellera approves new version of co-emulation modeling interface standard
May 2005
VSIA: New Book Defines Essential Terminology for the Electronics Industry
  EDA Confidential: This Verification Crisis is of Our Own Making
April 2005
VSIA: Taxonomies for the Development and Verification of Electronic Systems
April 2005
EETimes Asia: China beating U.S. in verification?
Feb 2005
EDA Nation: DVCon - Wally, Gary & Gabe
Feb 2005
EETimes: Wrestling functional verification
Feb 2005
EE Times: Will China beat the U.S. in verification?
Feb 2005
IEC Releases "The Functional Verification of Electronic Systems" Executive Editor: Brian Bailey
Feb 2005
EE Times: Verification requires new methodologies.
Feb 2005
Brian Bailey appointed to the Poseidon Design Technical Advisory Board.
Feb 2005
DesignCon 2005 - TechForum.. An Introduction to ESL (presentation)
Oct 2004
WSD FPGAs And Virtual Prototypes Share Common Design Space
Oct 2004
EE Times: Design complexity drives need for ESL
Sept 2004
EDA Confidential: Thoughts on Productivity
2004
Chip Design: Focus Report Sidebar: Hardware/Software Interfaces
2004
The Multiple Dimensions of Scalability that Comprise a System Verification Strategy
Mar 2004
EE Times "A new vision of 'scalable' verification"
Jun 2004
EDA Alert - "Making Assertions Work For Your Design Methodology"
Jun 2004
EEDesign Chinese
Nov 2003
EDAcentrum "Verification Languages and where they fit"
Oct 2003
EDN: Find and fix problems early in the design cycle
Sept 2003
Zaiq Technologies announces Prep 4.0
June 2003
Accellera Approves Four New Design Verification Standards
Jan 2003
EDACafe: Conflicting agendas create tension at DesignCon 2003
Jan 2002
DesignCon: Co-Verification: From Tool to Methodology
2002
Design and Verification German May/June
2000
Electronic News Interview - Dec 2000
May 2000 VSIA: Seamless Brief
Panels
Feb 2006
DesignCon - Why do so many chips fail?
Sept 2005
DesignCon East - The Role of Verification at the Architectural Definition Stage
Feb 2005
DesignCon 2005 Moderator - Are We Spending Our Verification Resources Wisely?
June 2004
Memocode: "The hurdles for acceptance of formal technologies" Video
June 2004

EE Times: Panelists debate phased implementation of SystemVerilog

Nov 2003
HLDVT: What's the Next 'Big Thing' in Simulation-Based Verification?
June 2002

DAC: Designers, providers weigh value of unified tools
PANEL: Unified Tools for SoC Embedded Systems: Mission Critical, Mission Impossible or Mission Irrelevant?

Mar 2002
ESC: Panelists debate the future of hardware design
Jan 2002
VSIA: VSIA’s SoC Forum at DesignCon 2002
VSIA ponders standards for software reuse
June 2001
DAC: verification is the key, but when?
June 1997
DAC: Hardware/Software co-verification
Citations

Helping companies improve their verification efficiency.

To request more information, please email me at brian_bailey@acm.org
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