Brian Bailey Consulting

I was born in England and lucky enough to attend Brunel University in West London for my undergraduate studies in Electrical and Electronic Engineering receiving a 1st class honours degree in 1981. While at Brunel, I got involved in the development of a tool called HILO, the worlds first commercial RTL simulator and soon became part of the development team. I worked on a large number of parts of that simulator, finally becoming the project and engineering manager for it in 1987.

Following that I got back into the hardware side of things for a while, working on the development of a RISC processor but then migrated back into the EDA world by working on hardware accelerators at Zycad. At Zycad I designed a system that unified the companies multiple hardware and software platforms and provided graphical front end tools to those platforms. This required the development of waveform languages and display systems, waveform comparison and sophisticated debug tools. This group was later acquired by Synopsys where the work continued.

In 1992 I joined Mentor as the technical lead for their multi-level, mixed signal simulation environment, which included an extension of the C language for behavioral modeling in the hardware space. Extending the notion of mixed environments then

took me into the hardware / software coverification space. With my role as technologist for this group, I also looked at it's extension into the system space, connection to emulators, embedded system development tools and many other directions. While the tool was successful capturing over 90% market share, its adoption was tepid. Wanting to learn more about the system design process, I started performing consulting to the companies end user companies.

As a consultant, I developed some ideal reference flows, helped companies identify the bottlenecks in their own flows and advised them on the ways that they could make improvements. Coupled with this work was an extensive education program intended to help engineering teams understand the changes that were going on in the industry.

During the course of my work, I have had four patents issued and others pending. I have been involved in a lot of standards groups, starting with the development of VHDL value sets, System design methodologies and simulation backplane technologies for CFI, numerous standards within the system level group of VSI, which I also chaired for a number of years and chaired the C language semantics group of Accellera. I am the current chair of the Accellera Interfaces Technical Committee which has successfully developed a co-emulation standard that is now getting widespread adoption in the market.

I have produced a number of papers, some of which are included on the press page, appeared on multiple panels and moderated others and been invited as a key note speaker at a number of events. I contributed to a book on SoC methodologies and have since published two books, the first is: The functional verification of digital systems, and the second: Taxonomy for the development and verification of electronic systems. In 2007 I published, along with Grant Martin and Andrew Piziali, what is becoming the definitive work on the Electronic System Level (ESL) Design and Verification space.

I am a reviewer, technical program member and track chair for a number of conferences, including DATE and DAC. I established a functional verification track in DesignCon which has quickly grown to become the track receiving most paper submissions.

I am currently a Technical Advisory Board member for Jasper Design Automation.